MIT develops cryptography chip capable of warding off malicious attacks
Image: MIT

 Quantum computing is no longer a far-off dream. Google, Microsoft, and Intel have all made significant strides in this area. Two months ago, IBM revealed its first quantum computer available for commercial use. The technology will enable unprecedented innovation and complex calculations that no classical computers can execute today.

However, the advent of quantum computing also means that hackers, too, will be able to harness its power. Consequently, cybersecurity will also have to improve in order to protect data that is exchanged between devices. This is especially true for Internet of Things (IoT) devices. Built for simple processing, they lack the sophistication to resist attacks from quantum computers.

Fortunately, Massachusetts Institute of Technology (MIT) researchers seem to have found a solution. The team has developed a small circuit that is able to run “lattice-based cryptography,” a highly complex wall of defense built on mathematical structures. The chips are integrable into any low-power IoT device. As such, they are able to ward off future malicious attacks. 

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Increased Sampling Efficiency

In their study, the researchers found that random number generation (“sampling”) and data storage were the two biggest hurdles to overcome with lattice-based cryptography. Both are crucial for successful cryptography schemes.

To overcome the sampling challenge, the team found one method. SHA-3 is 2-3 times more efficient than any others for generating pseudorandom numbers. After some minor adjustments, the SHA-3 became compatible with lattice-based cryptography sampling. The team also made postprocessing conversion much less resource intensive through the use of mathematical techniques.

The MIT research team’s circuit architecture meets the National Institute of Standards and Technology (NIST) lattice-based cryptography guidelines, a first for a chip of its size. The 2-millimeter wide circuit is a highly efficient piece of hardware. As such, it takes up less than 10 percent of the chip’s total surface area.

Using Less Space

Storing data generated by lattice-based cryptography typically requires 80 percent of hardware circuitry. Using “number theoretic transform” (NTT), a technique for splitting vector data into smaller pieces, the team was able to drastically reduce the amount of space needed to store data.

“We basically modified how the vector is physically mapped in the memory and modified the data flow,” says Utsav Banerjee, first author on the team’s research paper. “Using these architecture tricks, we reduced the energy consumption and occupied area, while maintaining the desired throughput.”

The team also incorporated a programmable memory component into the circuit so it can process different sampling techniques.

As lattice-based cryptography schemes evolve over time, this feature will become more and more valuable. Looking ahead, the MIT researchers aim to improve on their chip’s design so that it can run additional lattice-based cryptography schemes.

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